1. Field of the Invention
The present invention is directed to a plastic molded pin grid chip carrier package, and more particularly to a plastic molded chip carrier package having an increased number of I/O pins arranged in a pin grid array.
2. Description of the Prior Art
Pin grid array packages for semiconductor chips have been widely accepted in the art to replace ceramic packages for their feasibility of incorporating a plurality of I/O pins at the time of molding the package and for thermal compatibility with a conventional printed-circuit boards on which the packages are frequently required to be directly mounted. Such pin grid array plastic packages have been proposed, for example, in U.S. Pat. No. 4,618,739 in which a chip carrier is molded from a suitable plastic material to integrally include a plurality of I/O pins.
Now that there is an increasing industry demand to utilize more sophisticated integrated chips provided with a greater number of I/O ports, the conventional pin grid array configuration as in the above patent will encounter a critical problem when adding or increasing the number of I/O pins while retaining the pin density as high as possible to prevent the package from becoming too large. The problem is that, as the number of rows on the pin grid is increased to give a greater number of I/O pins in compliance with the increased I/O ports on the chip but without substantially increasing the pin pitch in each row, the electrical interconnection between the I/O ports on the chip and the individual I/O pins requires an elaborate wiring or connection technique, which is rather difficult to be realized on the pin grid array even with a standard pin pitch of 100 mil. That is, when the package is intended to have a plurality of rows on the pin grid in each of which the pins are closely spaced, it is very likely that the wires or connection lines extending from the I/O pins in the inner row of the pin grid cross or intersect with those from the outer row of the pin grid, making the electrical connection totally unreliable. With this result, the prior pin grid array package has a certain limitation on increasing the number of rows on the pin grid array, making the package unsatisfactory when it is required to further increase the number of I/O pin without substantially increasing the pin pitch.